kiến trúc máy tính giới thiệu chung về máy tính điện tử

103 NV Tam, HT Cc. IOIT, VAST Kin trỳc Mỏy tớnh CPUvohuong Lenh vo huong Lenh vector CU-Donvi diờukhiờn Pipe 1 Pipe Pipe 2 Du lieu M1 M2 n lenh tu bonho Mm Trong kin trỳc ny cú hai CPU chớnh: mt CPU vụ hng, v mt CPU vector. C hai nhn lnh t CU. CPU vector kim soỏt thc hin cỏc lnh vector bng cỏc ng dn, cũn CPU vụ hng thc hin lnh nh cỏc CPU thụng thng. CU ly lnh t b nh, gii mó lnh v tu loi lnh s chuyn cho cỏc CPU. 7. Systolic array: Bao gm s lng ln cỏc thnh phn x lớ ging nh nhau (processing elemtne PE). Mi PE cú b nh gioội hn, v khụng gii hn s PE, mi PE chie c ni n cỏc lỏng ging ca nú bi mng IN. Nh vy ta nhn thy cỏch ni ging kin trỳc ng ng, vớ d nh trng tuyn tớnh hay trng hai chiu. Trong h thng ny, cỏc d liu hay cỏc kt qu tng phn i qua cỏc PE trong thi gian thc hin ca mt vi chu kỡ x lớ. mi chu kỡ, mt s PE thc hin mt s cỏc thao tỏc nh sanhu (vớ d nh nhõn hay chia) trờn cỏc d liu ca cỏc PE ú, v gi cỏc kt qu tng phn ti cỏc PE lỏng ging. 113 NV Tam, HT Cc. IOIT, VAST Kin trỳc Mỏy tớnh PE PE PE PE PE PE IN IN Dau vao Dau ra PE PE PE 8. Hybrid architecture: L kt hp cỏc c thự ca cỏc kin trỳc khỏc nhau to ra hiu nng tt nht cho tớnh toỏn song song. Cú hai kiu tớnh toỏn song song: - kim soỏt song song: hai hay nhiu tớnh toỏn (operatons) thc hin ng thi trờn cỏc CPU khỏc nhau; - d liu song song: cựng mt tớnh toỏn thc hin trờn cỏc phn ca d liu bi nhiu CPU ng thi. MIMD l mụ hỡnh lớ tng ca kim soỏt song song,nú thớch hp cho bi toỏn cn nhiu tớnh toỏn khỏc nhau thc hin ng thi trờn mt d liu tỏch bit. Mỏy SIMD thớch hp cho xu lớ x lớ s liu song song, thớch hp cho bi toỏn kiu cựng mt thao tỏc x lớ ng thi trờn cỏc phn khỏc nhau ca mt d liu. SIMD h tr x lớ vector qua thit k ng ng. Trong thc t x lớ d liu song song l rt ln, vỡ quỏ trỡnh ú t l vi lng d liu a vo tớnh toỏn. Tuy nhiờn khụng phi lỳc no gii phỏp ny cng thnh cụng, do ú cn s dng phi hp c hai cỏch núi trờn. Vớ d, mt s ng dng chy tt khi chia chia nh mi phn ca ng dng dựng x lớ d liu song song, trong khi tt c cỏc phn li chy theo kiu kim si\oỏt song song theo kin trỳc ng. Mt nhúm cỏc CPU ly d liu, thc hin cỏc tớnh toỏn ban u, sau ú chuyn kt qu cho nhosm th hai, v nhúm hai tớnh toỏn, chuyn tip cho ti khi cú kt qu cui. Cỏc mỏy kt hp c hai MIMD v SIMD, cho hiu qu ỏng ghi nhn. 9. Cỏc thit b c bit 9.1 Mng neuron nhõn to (Artificial neural network (ANN)): c xõy dng t vụ s cỏc thnh phn tớnh toỏn hot ng song song, cú kh nng hc v t thớch nghi vi s thay i ca mụi trng tớnh toỏn v ng u vi hn lon. Cu trỳc mng neuron nhõn to ha hn gii quyt c cỏc vn m mỏy von Neumann khú cú th thc hin c (vớ d nh mụ phng thụng tin t nhiờn, nhn dng mu gene, nhng vn cn cú nng lc tớnh toỏn kiu con ngi mi thc hin c). Kin trỳc Mỏy tớnh 123 NV Tam, HT Cc. IOIT, VAST PE PE ..... PE PE PE ..... PE PE PE ..... PE Dauvao Daura Mi mt PE bt chc mt vi c tớnh ca neuron sinh hc, chỳng cú mt tp cỏc u vo, v mt hay vi u ra. Mi u vo c gỏn mt trng lng s. Trng lng ny tng t nh nng tip hp (synaptic strength) ca neuron sinh hc. Tt c cỏc u vo ca mi PE c bi lờn bng trng lng v sau ú cng li xỏc nh mc hot ng ca neuron. Mt mc hot ng l mt chc nng, gi l chc nng hot ng, c dựng to mt u ra (tớn hiu ra). u ra ca mt lp l u vo ca lp tip theo, v ti ú chỳng c cng li, ỏnh giỏ, to u ra. Quỏ trỡnh ny i qua ton mng neuron tỡm c mt quyt nh cui cựng no ú. Khụng ging nh von Neumann, trong ú thnh phn c bn l CPU, ANN l kin trỳc kt ni (mng neuron) gia cỏc PE. Vi mt bi toỏn cho trc, ta cn xỏc nh giỏ tr chớnh xỏc cho cỏc trng lng mng cú th thc hin cỏc tớnh toỏn cn thit. Thụng thng vic xỏc nh giỏ tr c tin hnh bng phng phỏp iu chnh tng tỏc ca trng lng theo hng ci thin hiu nng ca mng neuron. Lut iu chnh trng lng gi l lut hc (learning rule) v ton b quỏ trỡnh cú c giỏ tr chớnh xỏc ca trng lng gi l quỏ trỡnh hc (learning). 9.2 Logic m (Fuzzy logic processor): l cỏc nguyờn lớ hỡnh thc ca lp lun gn ỳng. Trong khi trc õy ta cú lp lun hai giỏ tr (true v false). Logic m n lc gii quyt hiu qu vi tớnh phc tp ca quỏ trỡnh nhn thc ca con ngi, v nú vt qua mt s cỏc phin phc phi hp vi logic nh nguyờn c in khụng th phn ỏnh c quỏ trỡnh nhn thc thc ca con ngi. Tuy cỏc phn mm phỏt trin trờn logic m mang li mt s kt qu t cho vi ng dng, thỡ cỏc ng dng hiu nng cao ang cn cỏc b x lớ logic m chuyờn dng. 1.2.2. Processor performance The performance of the processor, which can be considered as the central nervous system of the units that compose the computer system, is measured using the number of instructions that can be executedd in a unit of time as an index. These indexes are indicated below. (1) MIPS Kin trỳc Mỏy tớnh 133 NV Tam, HT Cc. IOIT, VAST MIPS is an acronym of Million Instructions Per Second, and indicates in million units the number of instructions that can be executed in one second. In other words, a 1 MIPS processor is a processor that can execute one million instructions per second. Basically, the larger the number of instructions that can be executed, the higher the value. The term MIPS is mainly used to indicate the performance of processors of high end mainframe computers. However, it is meaningless to use this index to compare processors of different types of machines that execute different instruction contents. (3) FLOP Floating operation (3) Clock In order to set the pace in which the micro-instructions, which are basic operations, are executed, the processor has a click inside. A quartz crystal oscillator that pulses in regular intervals when electrical current passes through is sued in this clock. The time taken for this oscillator to pulse once (one cycle) is called click, The basic operations of the processor are performed according to this clock. The number of clocks varies according to the instruction. The clock reciprocal number is called clock frequency. Clock frequency is used as an index to measure the performance of a personal computer. (4) CPI (Cycles Per Instruction) A CPI is the number of clocks required to execute instruction This index indirectly indicates the execution time of one instruction Literature Architecture: John L. Hennessy and David A. Patterson, Computer Architecture: A Quantitative Approach, third edition, Morgan Kaufmann, New York, 2003. See www.mkp.com/CA3. David A. Patterson and John L. Hennessy, Computer Organization and Design: The Hardware Interface. Text for COEN 171. Gerrit A. Blaauw and Frederick P. Brooks, Jr., Computer Archtecture: Concepts and Evolution, Addison Wesley, 1997. Kin trỳc Mỏy tớnh 143 NV Tam, HT Cc. IOIT, VAST William Stallings, Computer Organization and Architecture, Prentice Hall, 2000. Miles J. Murdocca and Vincent P. Heuring, Principles of Computer Architecture, Prentice Hall, 2000. John D. Carpinelli, Computer Systems Organization and Architecture, Addison Wesley, 2001. Davis A. Palterson & John L. Hannesy, Computer Organization and design: The hardware / Software interface, 1998. Andrew S Tanenbaun, Structred Computer Organization, 4th,1998.James M. feldman, Charles T. Retter, Computer Architecture Adesignned text based on generic RISC. 1994. Kin trỳc Mỏy tớnh 153 NV Tam, HT Cc. IOIT, VAST 1.3. Mỏy tớnh mu Mỏy tớnh in t n gin c mụ t di cỏc mc khỏc nhau: 1 S khi 2 S kin trỳc 3 S vn chuyn gia cỏc thanh ghi 4 S mch logic bc thp 5 S cỏc mch in t 1.3.1. S khi ca mỏy tớnh mu Mỏy tớnh mu (hỡnh 1.3 v hỡnh 1.4) ny c mụ phng theo mt mỏy tớnh ca trng i hc Virginia Technology nhm mc ớch trang b nhng khỏi nim c bn ban u nhp mụn vo cu trỳc mỏy tớnh.